The present invention relates broadly to a memory test apparatus, and in particular to a micro-coded built-in self-test apparatus for a memory cell array.
In the prior art, a variety of techniques have been utilized to provide built-in self-test (BIST) of memory devices employed random logic to define the type of memory test to be performed on cells in the array. A disadvantage of the random logic approach is that it allows only a specific test to be run on a memory device unless a complete redesign of the random logic is performed. Limitations on memory test algorithm complexity becomes significant for complex memory test algorithms. In addition, random logic devices are poor performers for data retention tests from the perspective of chip area for BIST.
While the prior art approaches to providing built-in self-test circuits have been functional, it is quite clear that there remains a need to provide a built-in self-test apparatus for random access memory arrays. The present invention is intended to satisfy that need.